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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel 978-250-3373 fax Order On-line at www.hittite.com
Application Support: apps@hittite.com
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HMC700LP4 / 700LP4E
v11.0411
8 GHz 16-Bit Fractional-N PLL
PFD Lock Detect (Continued)
Figure 12. Delayed Lock Detect Window
Cycle Slip Prevention (CSP)
When the Vco is not yet locked to the reference, the instantaneous frequencies of the two paths are different, and
the phase difference of the two paths at the PFD varies rapidly over a range much greater than ±2π radians. Since
the gain of the PFD varies linearly with phase up to ±2π, the gain of a conventional PFD will cycle from high gain,
when the phase difference approaches a multiple of 2π, to low gain, when the phase difference is slightly larger than
a multiple of 0 radians. the charge on the loop filter small cap may actually discharge slightly during the low gain
portion of the cycle. this can make the Vco frequency actually reverse temporarily during locking. this phenomena
is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown
in the red curve in Figure 13, and increases the time to lock to a value far greater than that predicted by normal small
signal Laplace analysis.
the HMc700LP4(E) PFD features an ability to virtually eliminate cycle slipping during acquisition. When enabled,
the cycle Slip Prevention (cSP) feature essentially holds the PFD gain at maximum until such time as the frequency
difference is near zero. cycle Slip Prevention, allows faster lock times as shown in Figure 13. the use of the cycle slip
feature is enabled with csp_enable (see table 14) .
the cycle Slip Prevention feature may be optimized for a given set of PLL dynamics by adjusting the PFD sensitivity
to cycle slipping. this is achieved by adjusting csp_corr_magn in table 13.
Figure 13. Cycle Slip Prevention (CSP)
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